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The next major decision is how to lay out the caches Because the cost of accessing main memory is so costly and can saturate the bus (which can eas ily become a bottleneck when more and more processors are added to the system), it is attractive for computer architects to add several levels of caching Registers are the most extreme form of caching; it's just that compilers are responsible for managing their contents instead of the hardware The stan dard naming for such levels are LI , L2, L3, and so on; the smaller the num ber, the closer it is to the processor core, the smaller the size, and the faster it tends to be L 1 cache typically occupies on-die space, so that the processor can access it very quickly; but this means the capacity is quite limited

On-die cache typically consists of two separate caches: an I-cache and a D-cache, responsible for caching program instructions issued to the processor and data, respectively SMP machines are often laid out such that each processor gets a reasonably sized L1 cache, and an L2 cache is shared among all the different processors CMP machines are slightly different Because multiple processors share the same die space, it can be attractive to give each (or some portion of them) inde pendent L1 caches It can also be attractive to share even more die space for an L2 cache shared among them all and to have an off-die L3 This is where you will see the most creative freedom applied by processor architects, both today and in the future Another design decision for cache design is the cache-line size This is the smallest unit of memory that can be transferred to and from main memory On most Intel machines lines are 64 bytes in size, while most AMD machines use cache lines that are 1 28 bytes in size Line sizes can even change from one level in the cache to the next; for example, some Intel machines in the past used 1 28 bytes for L2 cache and only 64 bytes for L1 caches An example of a cache hierarchy is shown in Figure 1 4 1 In this illus tration, a hypothetical 4-processor SMP system is depicted in which each processor has its own local L1 cache (lMB each) and a single level of L2 shared cache ( l 6MB), caching data which comes from the shared main memory (l CB) This is a fairly typical layout for modern SMP machines

Payroll Journal Entries / 205

Processor 2 Shared P 1 's L 1 Cache (1 MB) P2's L 1 Cache (1 MB) ( I nterconnect) P3's L1 Cache (1 MB) P4's L 1 Cache (1 MB) Processor 4

We have introduced some basic ideas regarding statistical inference the process by which we draw inferences from samples using con dence intervals or hypothesis testing We will continue our discussion of statistical inference in the next chapter where we look at the situation when nothing is known about the population being sampled We will also learn about comparing two samples drawn from possibly different populations

(4 GB)

1 0,000,000 1 ,000,000 1 00,000 1 0,000 1 ,000 1 00 1

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1 Use a computer to select 100 samples of size 5 each from a N(0, 1) distribution Compute the mean of each sample and then nd how many of these are within the interval 073567 and 073567 How many means are expected to be in this interval 2 In the past, 20% of the production of a sensitive component is unsatisfactory A sample of 20 components shows 6 items that must be reworked The manufacturer is concerned that the percentage of components that must be reworked has increased to 30% (a) Form appropriate null and alternative hypotheses (b) Let X denote the number of items in a sample that must be reworked If the critical region is {x | x 9}, nd the sizes of both Type I and Type II errors (c) Choose other critical regions and discuss the implications of these on both types of errors